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LD7575
6/5/2007
Green-Mode PWM Controller with High-Voltage Start-Up Circuit
REV: 04a
General Description
The LD7575 is a current-mode PWM controller with excellent power-saving operation. It features a highvoltage current source to directly supply the startup current from bulk capacitor and further to provide a lossless startup circuit. The integrated functions such as the leading-edge blanking of the current sensing, internal slope compensation, and the small package provide the users a high efficiency, minimum external component counts, and low cost solution for AC/DC power applications. Furthermore, the embedded over voltage protection, over load protection and the special green-mode control provide the solution for users to design a high performance power circuit easily. DIP-8 package. The LD7575 is offered in both SOP-8 and
Features
High-Voltage (500V) Startup Circuit Current Mode Control Non-Audible-Noise Green Mode Control UVLO (Under Voltage Lockout) LEB (Leading-Edge Blanking) on CS Pin Programmable Switching Frequency Internal Slope Compensation OVP (Over Voltage Protection) on Vcc OLP (Over Load Protection) 500mA Driving Capability
Applications
Switching AC/DC Adapter and Battery Charger Open Frame Switching Power Supply LCD Monitor/TV Power
Typical Application
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Pin Configuration
SOP-8 & DIP-8 (TOP VIEW) VCC
6
8
7
OUT
5
NC
HV
TOP MARK YYWWPP
1 2 3 4
YY: WW: PP:
Year code Week code Production code
RT
COMP
Ordering Information
Part number LD7575 PS LD7575 PN Package SOP-8 DIP-8 Top Mark LD7575PS LD7575PN Shipping 2500 /tape & reel 3600 /tube /Carton
The LD7575 is ROHS compliant.
Pin Descriptions
PIN 1 NAME RT FUNCTION This pin is to program the switching frequency. By connecting a resistor to ground to set the switching frequency. Voltage feedback pin (same as the COMP pin in UC384X), By connecting a photo-coupler to close the control loop and achieve the regulation. Current sense pin, connect to sense the MOSFET current Ground Gate drive output to drive the external MOSFET Supply voltage pin Unconnected Pin Connect this pin to positive terminal of bulk capacitor to provide the startup current 8 HV for the controller. When Vcc voltage trips the UVLO(on), this HV loop will be off to save the power loss on the startup circuit.
2 3 4 5 6 7
COMP CS GND OUT VCC NC
GND
CS
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Block Diagram
HV
1mA 8V POR
32V 16.0V/ 10.0V
UVLO Comparator
OVP Comparator
VCC
internal bias & Vref
VCC OK
27.5V
RT
OSC
PG
Vref OK
S
Q
R
Green-Mode Control Vbias OVP PG
S
Q
OLP
COMP
PWM Comparator 2R R
R
+ Slope Compensation POR 0.85V OCP Comparator
CS
Leading Edge Blanking
+
Driver Stage
OUT
clear
30mS Delay OLP Comparator /2 Counter
S
Q
5.0V
PG
R
GND
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Absolute Maximum Ratings
Supply Voltage VCC High-Voltage Pin, HV COMP, RT, CS Junction Temperature Operating Ambient Temperature Storage Temperature Range Package Thermal Resistance (SOP-8) Package Thermal Resistance (DIP-8) Power Dissipation (SOP-8, at Ambient Temperature = 85C) Power Dissipation (DIP-8, at Ambient Temperature = 85C) Lead temperature (Soldering, 10sec) ESD Voltage Protection, Human Body Model (except HV Pin) ESD Voltage Protection, Machine Model Gate Output Current 30V -0.3V~500V -0.3 ~7V 150C -40C to 85C -65C to 150C 160C/W 100C/W 400mW 650mW 260C 3KV 200V 500mA
Caution:
Stresses beyond the ratings specified in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions
Item Supply Voltage Vcc Vcc Capacitor Switching Frequency Min. 11 10 50 Max. 25 47 130 Unit V F KHz
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Electrical Characteristics
(TA = +25 C unless otherwise stated, VCC=15.0V) PARAMETER High-Voltage Supply (HV Pin) High-Voltage Current Source Off-State Leakage Current Supply Voltage (Vcc Pin) Startup Current Operating Current (with 1nF load on OUT pin) UVLO (off) UVLO (on) OVP Level Voltage Feedback (Comp Pin) Short Circuit Current Open Loop Voltage Green Mode Threshold VCOMP Current Sensing (CS Pin) Maximum Input Voltage Leading Edge Blanking Time Input impedance Delay to Output Oscillator (RT pin) Frequency Green Mode Frequency Temp. Stability Voltage Stability Gate Drive Output (OUT Pin) Output Low Level Output High Level Rising Time Falling Time OLP (Over Load Protection) OLP Trip Level OLP Delay Time (note) Fs=65KHz 5.0 30 V mS VCC=15V, Io=20mA VCC=15V, Io=20mA Load Capacitance=1000pF Load Capacitance=1000pF 9 50 30 160 60 1 V V nS nS RT=100K Fs=65.0KHz (-40C ~105C) (VCC=11V-25V) 60.0 65.0 20 3 1 70.0 KHz KHz % % 1 100 0.80 0.85 350 0.90 V nS M nS VCOMP=0V COMP pin open 1.5 6.0 2.35 2.2 mA V V VCOMP=0V VCOMP=3V Protection tripped (OLP, OVP) 9.0 15.0 25.0 2.0 2.5 0.5 10.0 16.0 27.5 11.0 17.0 30.0 100 3.0 4.0 A mA mA mA V V V Vcc< UVLO(on), HV=500V Vcc> UVLO(off), HV=500V 0.5 1.0 1.5 35 mA A CONDITIONS MIN TYP MAX UNITS
o
Note: The OLP delay time is proportional to the period of switching cycle. frequency and the shorter OLP delay time.
So that, the lower RT value will set the higher switching
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Typical Performance Characteristics
1.5 0.90
HV Current Source (mA)
1.3
0.89
VCS (off) (V)
0 40 80 120 125
0.88
1.1
0.87
0.9 0.86
0.7 -40
0.85
-40
0
40
80
120
125
Temperature (C) Fig. 1 HV Current Source vs. Temperature (HV=500V, Vcc=0V)
18.0 12
Fig. 2
Temperature (C) VCS (off) vs. Temperature
17.2
11.2
UVLO (on) (V)
UVLO (off) (V)
-40 0 40 80 120 125
16.4
10.4
15.6
9.6
14.8
8.8
14.0
8 -40 0 40 80 120 125
Temperature (C) Fig. 3 UVLO (on) vs. Temperature
70 26
Temperature (C) Fig. 4 UVLO (off ) vs. Temperature
68
24
Frequency (KHz)
-40 0 40 80 120 125
Frequency (KHz)
66
22
64
20
62
18
60
16 -40 0 40 80 120 125
Temperature (C) Fig. 5 Frequency vs. Temperature
Temperature (C) Fig. 6 Green Mode Frequency vs. Temperature
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70 25
68
Green mode frequency (KHz)
12 14 16 18 20 22 24 25
23
Frequency (KHz)
66
21
64
19
62
17
60 11
15 11
12
14
16
18
20
22
24
25
Vcc (V) Fig. 7 Frequency vs. Vcc
85 35
Vcc (V) Fig. 8 Green mode frequency vs. Vcc
80
30
Max Duty (%)
75
VCC OVP (V)
-40 0 40 80 120 125
25
70
20
65
15
60
10 -40 0 40 80 120 125
Temperature (C) Fig. 9 Max Duty vs. Temperature
7.0 6.0
Temperature (C) Fig. 10 VCC OVP vs. Temperature
6.5
5.5
VCOMP (V)
5.5
OLP (V)
-40 0 40 80 120 125
6.0
5.0
4.5
5.0
4.0
4.5
3.5 -40 0 40 80 120 125
Temperature (C) Fig. 11 VCOMP open loop voltage vs. Temperature Fig. 12
Temperature (C) OLP-Trip Level vs. Temperature
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Application Information
Operation Overview
As long as the green power requirement becomes a trend and the power saving is getting more and more important for the switching power supplies and switching adaptors, the traditional PWM controllers are not able to support such new requirements. Furthermore, the cost and size limitation force the PWM controllers need to be powerful to integrate more functions to reduce the external part counts. The LD7575 is targeted on such application to provide an easy and cost effective solution; its detail features are described as below: threshold thus the current source is on to supply a current with 1mA. Meanwhile, the Vcc supply current is as low as 100A thus most of the HV current is utilized to charge the Vcc capacitor. By using such configuration, the turn-on delay time will be almost same no matter under low-line or high-line conditions. Whenever the Vcc voltage is higher than UVLO(on) to power on the LD7575 and further to deliver the gate drive signal, the high-voltage current source is off and the supply current is provided from the auxiliary winding of the transformer. achieved. An UVLO comparator is included to detect the voltage on the Vcc pin to ensure the supply voltage enough to power
Vin
Therefore, the power losses on the startup
circuit can be eliminated and the power saving can be easily
Internal High-Voltage Startup Circuit and Under Voltage Lockout (UVLO)
on the LD7575 PWM controller and in addition to drive the power MOSFET.
Cbulk R1 D1
As shown in Fig. 14, a hysteresis is
provided to prevent the shutdown from the voltage dip during startup. The turn-on and turn-off threshold level are set at 16V and 10.0V, respectively.
C1
Vcc
HV VCC OUT
LD7575
Comp GND CS
UVLO(on) UVLO(off)
Rs
t
Fig. 13 Traditional circuit powers up the PWM controller through a startup resistor to provide the startup current. However, the startup resistor consumes significant power which is more and more critical whenever the power saving requirement is coming tight. Theoretically, this startup resistor can be
HV Current
1mA
~ 0mA (off)
t Vcc current
Operating Current (Supply from Auxiliary Winding) Startup Current (<100uA)
very high resistance value. However, higher resistor value will cause longer startup time. To achieve an optimized topology, as shown in figure 13, LD7575 implements a high-voltage startup circuit for such requirement. During the startup, a high-voltage current source sinks current from the bulk capacitor to provide the startup current as well as charge the Vcc capacitor C1. During the startup transient, the Vcc is lower than the UVLO
Fig. 14
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Current Sensing, Leading-edge Blanking and the Negative Spike on CS Pin
The typical current mode PWM controller feedbacks both current signal and voltage signal to close the control loop and achieve regulation. The LD7575 detects the primary MOSFET current from the CS pin, which is not only for the peak current mode control but also for the pulse-by-pulse current limit. The maximum voltage threshold of the current sensing pin is set as 0.85V. Thus the MOSFET peak current can be calculated as:
IPEAK(MAX) = 0.85 V RS
A 350nS leading-edge blanking (LEB) time is included in the input of CS pin to prevent the false-trigger caused by the current spike. In the low power application, if the total pulse width of the turn-on spikes is less than 350nS and the negative spike on the CS pin is not exceed -0.3V, the R-C filter (as shown in figure15) can be eliminated. However, the total pulse width of the turn-on spike is related to the output power, circuit design and PCB layout. It is strongly recommended to add the small R-C filter (as shown in figure 16) for higher power application to avoid the CS pin damaged by the negative turn-on spike.
Fig. 15
Output Stage and Maximum Duty-Cycle
An output stage of a CMOS buffer, with typical 500mA driving capability, is incorporated to drive a power MOSFET directly. And the maximum duty-cycle of LD7575 is limited to 75% to avoid the transformer saturation.
Voltage Feedback Loop
The voltage feedback signal is provided from the TL431 in the secondary side through the photo-coupler to the COMP pin of LD7575. The input stage of LD7575, like the UC384X, is with 2 diodes voltage offset then feeding into the voltage divider with 1/3 ratio, that is,
V+ (PWM COMPARATOR ) = 1 x ( VCOMP - 2VF ) 3
A pull-high resistor is embedded internally thus can be eliminated on the external circuit.
Fig. 16
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Oscillator and Switching Frequency
Connecting a resistor from RT pin to GND according to the equation can program the normal switching frequency:
fSW = 65.0 x 100(KHz) RT(K )
threshold 5.0V and keeps longer than 30mS (when switching frequency is 65KHz), the protection is activated and then turns off the gate output to stop the switching of power circuit. The 30mS delay time is to prevent the false trigger from the power-on and turn-off transient. A divide-2 counter is implemented to reduce the average power under OLP behavior. Whenever OLP is activated, The latch is released if the output is latched off and the divide-2 counter starts to count the number of UVLO(off). recovery to switching again. By using such protection mechanism, the average input power can be reduced to very low level so that the component temperature and stress can be controlled within the safe operating area. the 2nd UVLO(off) point is counted then the output is
The suggested operating frequency range of LD7575 is within 50KHz to 130KHz.
Internal Slope Compensation
A fundamental issue of current mode control is the stability problem when its duty-cycle is operated more than 50%. To stabilize the control loop, the slope compensation is needed in the traditional UC384X design by injecting the ramp signal from the RT/CT pin through a coupling capacitor. In LD7575, the internal slope compensation circuit has been implemented to simplify the external circuit design.
On/Off Control
The LD7575 can be controlled to turn off by pulling COMP pin to lower than 1.2V. The gate output pin of LD7575 will be disabled immediately under such condition. The off mode can be released when the pull-low signal is removed.
Dual-Oscillator Green-Mode Operation
There saving are many difference such as topologies has been implemented in different chips for the green-mode or power requirements "burst-mode control", "skipping-cycle Mode", "variable off-time control "...etc. The basic operation theory of all these approaches intended to reduce the switching cycles under light-load or no-load condition either by skipping some switching pulses or reduce the switching frequency.
Fig. 17
OVP (Over Voltage Protection) on Vcc
The Vgs ratings of the nowadays power MOSFETs are most
Over Load Protection (OLP)
To protect the circuit from the damage during over load condition or short condition, a smart OLP function is implemented in the LD7575. Figure 17 shows the waveforms of the OLP operation. Under such fault condition, the feedback system will force the voltage loop toward the saturation and thus pull the voltage on COMP pin (VCOMP) to high. Whenever the VCOMP trips the OLP
with maximum 30V. To prevent the Vgs from the fault condition, LD7575 is implemented an OVP function on Vcc. Whenever the Vcc voltage is higher than the OVP threshold voltage, the output gate drive circuit will be shutdown simultaneous thus to stop the switching of the power MOSFET until the next UVLO(on). The Vcc OVP function in LD7575 is an auto-recovery type protection. If the OVP condition, usually caused by the
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feedback loop opened, is not released, the Vcc will tripped the OVP level again and re-shutdown the output. is working as a hiccup mode. operation. On the other hand, if the OVP condition is removed, the Vcc level will get back to normal level and the output is automatically returned to the normal operation. The Vcc Figure 18 shows its This external pull-low resistor is to prevent the MOSFET from damage during power-on under the gate resistor is disconnected. In such single-fault condition, as show in figure 21, the resistor R8 can provide a discharge path to avoid the MOSFET from being false-triggered by the current through the gate-to-drain capacitor Cgd. Therefore, the MOSFET is always pull-low and kept in the off-state whenever the gate resistor is disconnected or opened in any case.
VCC
OVP Tripped OVP Level UVLO(on) UVLO(off)
t OUT
Switching
Non-Switching
Switching
t
Fig. 18
Fault Protection
A lot of protection features have been implemented in the LD7575 to prevent the power supply or adapter from being damaged caused by single fault condition on the open or short condition on the pin of LD7575. Under the conditions listed below, the gate output will be off immediately to protect the power circuit --RT pin short to ground RT pin floating CS pin floating
Fig. 19
Pull-Low Resistor on the Gate Pin of MOSFET
In LD7575, an anti-floating resistor is implemented on the OUT pin to prevent the output from any uncertain state which may causes the MOSFET working abnormally or false triggered-on. However, such design won't cover the condition of disconnection of gate resistor Rg thus it is still strongly recommended to have a resistor connected on the MOSFET gate terminal (as shown in figure 19) to provide extra protection for fault condition.
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Protection Resistor on the Hi-V Path
In some other Hi-V process and design, there may cause a parasitic SCR between HV pin, Vcc and GND. As shown in figure 22, a small negative spike on the HV pin may trigger this parasitic SCR and causes the latchup between
dV i = Cgd bulk dt
Vcc and GND.
And such latchup is easy to damage the
chip because of the equivalent short-circuit which is induced by such latchup behavior. Thanks to the Leadtrend's proprietary Hi-V technology, there is no such parasitic SCR in LD7575. Figure 23 shows the equivalent circuit of LD7575's Hi-V structure. So that LD7575 is with higher capability to sustain negative voltage than similar products. However, a 10K resistor is recommended to implement on the Hi-V path to be played the role as a current limit resistor whenever a negative voltage is applied in any case.
Fig. 20
Fig. 21
Fig. 22
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Reference Application Circuit --- 10W (5V/2A) Adapter
Pin < 0.15W when Pout = 0W & Vin = 264Vac
Schematic
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LD7575
BOM
P/N Component Value Original P/N Component Value Note
R1A R1B R4A R4B R6 R7 R8 R9 RS1 RS2 RT R51A R51B R52 R53 R54 R55 R56A R56B NTC1 FL1 T1 L51
N/A N/A 39K, 1206 39K, 1206 2.2, 1206 10, 1206 10K, 1206 10K, 1206 2.7, 1206, 1% 2.7, 1206, 1% 100K, 0805, 1% 100, 1206 100, 1206 2.49K, 0805, 1% 2.49K, 0805, 1% 100, 0805 1K, 0805 2.7K, 1206 N/A 5, 3A 20mH EI-22 2.7H 08SP005 UU9.8
C1 C2 C4 C5 C51 C52 C54 C55 CX1 CY1 D1A D1B D1C D1D D2 D4 Q1 CR51 ZD51 IC1 IC2 IC51 F1 Z1
22F, 400V 22F, 50V 1000pF, 1000V, 1206 0.01F, 16V, 0805 1000pF, 50V, 0805 1000F, 10V 470F, 10V 0.022F, 16V, 0805 0.1F 2200pF 1N4007 1N4007 1N4007 1N4007 PS102R 1N4007 2N60B SB540 6V2C LD7575PS EL817B TL431 250V, 1A N/A
L-tec L-tec Holystone
L-tec L-tec X-cap Y-cap
600V, 2A
SOP-8 1%
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Package Information
SOP-8
Dimensions in Millimeters Symbols MIN
A B C D F H I J M 4.801 3.810 1.346 0.330 1.194 0.178 0.102 5.791 0.406 0
Dimensions in Inch MIN
0.189 0.150 0.053 0.013 0.047 0.007 0.004 0.228 0.016 0
MAX
5.004 3.988 1.753 0.508 1.346 0.229 0.254 6.198 1.270 8
MAX
0.197 0.157 0.069 0.020 0.053 0.009 0.010 0.244 0.050 8
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Package Information
DIP-8
Dimension in Millimeters Symbol Min Max
Dimensions in Inches Min Max
A B C D E F I J L
9.017 6.096 ----0.356 1.143 2.337 2.921 7.366 0.381
10.160 7.112 5.334 0.584 1.778 2.743 3.556 8.255 ------
0.355 0.240 -----0.014 0.045 0.092 0.115 0.29 0.015
0.400 0.280 0.210 0.023 0.070 0.108 0.140 0.325 --------
Important Notice
Leadtrend Technology Corp. reserves the right to make changes or corrections to its products at any time without notice. Customers should verify the datasheets are current and complete before placing order.
0
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Revision History
Rev. 00 01 Date 07/21/'05 07/28/'05 Change Notice Original Specification. 1. 2. Page 2, Remove the unexpected code "skype.lnk" before the "ordering information". Page 4, Recommended operating condition, change the "min. supply voltage Vcc" from 10V to 11V since the UVLO range is from 9V to 11V. 3. 4. Page 9, Add the gate resistor on figure 15 and figure 16 to avoid misunderstanding. Page 11, Add the description "Figure 17 shows its operation." In the section of "OVP on Vcc". 5. 02 10/24/'05 1. Page 13, Add "Vin=264Vac" on the title. Add DIP-8 Package a. Page 1 --- modify the general description "The LD7575 is offered in both SOP-8 and DIP-8 package.". b. Page 2 --- Add DIP-8 data on the "pin configuration" and "ordering information". c. d. 2. Page 4 --- Add DIP-8 data on the "absolute maximum rating". Page 15 --- Add DIP-8 package drawing
Add information of HV current limit resistor and gate-to-GND resistor a. Page 1, 8 (figure13), 9 (figure15,16), 12, 13 --- Update the drawing, BOM and schematics for such resistors. b. Page 11, 12 --- Add the sections "Pull-Low Resistor on the Gate Pin of MOSFET", "Protection Resistor on the Hi-V Path" and figure 19~22. c. Page 4 --- Add negative voltage limitation of HV pin on the "absolute maximum rating".
3.
Correction on the block diagram a. Page 3 --- Add flip-flop on the OVP loop to be matched with the OVP operation and add the anti-floating resistor on the output.
4.
Correction on the description of Over Load Protection (OLP) a. Page 10 --- Original description "Whenever....30mS (when switching frequency is 100KHz)". Where the "100KHz" should be corrected to "65KHz".
Continued...
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03 11/28/'05 1. Page3, Correction on the block diagram by modifying the AND gate (following the PWM comparator) to OR gate. 2. Page 5, Correction on the parameters on "Gate Drive Output" because LD7575 can support to 500mA driving capability but the parameters in the previous datasheet are for 300mA driving current. The output high level will be updated from min. 8V to min. 9V. The rising time will be updated from max. 200nS to max. 160nS. The falling time will be updated from max. 100nS to max. 60nS. All these parameters are for correction and no design change on the related circuits.
04 04a
1/22/'07 6/5/2007
Revision: Block Diagram HV=500V (supplement to HV current source/ off state leakage current)
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